AT697E_09 Datasheet, PDF (14/154 Pages) ATMEL Corporation – Rad-Hard 32 bit SPARC V8 Processor

AT697 CPU Core
SPARC Architecture
Overview
Fetch
Decode
Execute
Memory
Write
This section discusses the SPARC core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to access
memories, perform calculations, control peripherals, and handle interrupts.
The AT697 CPU core is based on the LEON2 architecture.
Figure 2. Block diagram of the AT697 Integer Unit architecture
I-cache
data address
d_inst
e_inst
call/branch address
+1
Add
‘0’ jmpa tbr
f_pc
d_pc
e_pc
imm, tbr, wim, psr
rs1
operand2
m_inst
w_inst
m_pc
w_pc
alu/shift
result
mul/div
y
ytmp
wres
Y
30
rd
regfile
rs1 rs2
tbr, wim, psr
32 _{ex pc}
30 _{jmpl address}
D-cache
32 _{address/dataout}
32 _datain
14 AT697E
The AT697 integer unit (IU) implements SPARC integer instructions as defined in
SPARC Architecture Manual version 8. The IU is designed for highly dependable space
and military applications by including fault tolerance features.
To execute instructions at a rate approaching one instruction per clock cycle, the IU
employs a five-stage instruction pipeline that permits parallel execution of multiple
instructions.
• Instruction Fetch: If the instruction cache is enabled, the instruction is fetched from
the instruction cache. Otherwise, the fetch is forwarded to the memory controller.
The instruction is valid at the end of this stage and is latched inside the IU.
• Decode: The instruction is decoded and the operands are read. Operands may
come from the register file or from internal data bypasses. CALL and Branch target
addresses are generated in this stage.
• Execute: ALU, logical, and shift operations are performed. For memory operations
and for JMPL/RETT, the address is generated.
• Memory: Data cache is accessed. For cache reads, the data will be valid by the end
of this stage, at which point it is aligned as appropriate. Store data read out in the
Execute stage is written to the data cache at this time.
4226G–AERO–05/09