AT697E_09 Datasheet, PDF (32/154 Pages) ATMEL Corporation – Rad-Hard 32 bit SPARC V8 Processor

SRAM Read Access
AT697
A read access to SRAM consists in two data cycles and between zero and three wait-
states. On non-consecutive accesses, a lead-out cycle is added after a read cycle to
prevent bus contention due to slow turn-off time of memories or I/O devices. On consec-
utive accesses, no lead-out cycle is performed between the acesses but only one is
performed at the end of the operations (RAMSN and RAMOE are not deasserted).
When a read access to SRAM is performed, a separate output enable signal is provided
for each SRAM bank and it is only asserted when that bank is selected.
Figure 10. SRAM read cycle (0-waitstate)
data1
CLK
A
A1
data2
lead-out
RAMS*
RAMOE*
D
D1
SRAM Write Access
Waitstates
4226G–AERO–05/09
Each byte lane has an individual write strobe (RAMWE*) to allow efficient byte and half-
word writes.
Each write access to SRAM consists of three cycles and between zero and three wait-
states. The three mandatory cycles are divided in one write setup cycle, one data cycle
and one lead-out cycle.
Figure 11. SRAM write cycle (0-waitstate)
lead-in
data
CLK
A
A1
lead-out
RAMS*
RWE*
D
D1
If the external memory use a common write strobe for the full 16- or 32-bit data, set the
read-modify-write bit MCFG2. This will enable read-modify-write cycles for sub-word
writes.
For application using slow SRAM memories, the SRAM controller provides the capability
to insert wait-states during the SRAM accesses. Two types of wait-states can be
inserted :
• Programmed delay, available for bank 0 up to bank 3
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