AT697E_09 Datasheet, PDF (120/154 Pages) ATMEL Corporation – Rad-Hard 32 bit SPARC V8 Processor

AT697
Bit Number
31..0
Mnemonic
start address
Description
PCI start address for PCI initiator transactions in APB and DMA mode.
Table 90. PCI Initiator Write Register - PCIIW
Address = 0x8000014C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
ben
r/w
r/w
0x0000 000
0x0
Bit Number
3..0
Mnemonic
ben
Description
Byte enables for writes to the PCI core configuration space
‘0’ = enabled
‘1’ = disabled
Each of the 4 bits is assigned to one 8-bit lane.
• bit ben[3] is applied to Byte 3, the most significant byte (MSB)
• bit ben[2] is applied to Byte 2
• bit ben[1] is applied to Byte 1
• bit ben[0] is applied to Byte 0, the less significant byte (LSB)
Table 91. PCI DMA configuration Register - PCIDMA
address = 0x80000150
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
com
wdcnt
Bit Number
12
11..8
7..0
r/w
0x0000 0
Mnemonic
b2b
com
wdcnt
r/w
0
0x0
r/w
0x00
Description
Use back2back-mode.
Can be written to 1, if this transaction is to the same target, as the last one.
Note: works only, if the core is enabled for back2back mode.
PCI command to be used in DMA mode.
Word count.
Minimum number of words for the burst.
4226G–AERO–05/09
119