AT91RM9200_09 Datasheet, PDF (676/701 Pages) ATMEL Corporation – ARM920T-based Microcontroller

41.8 SDRAMC
41.8.1
SDRC_IMR can be written
The Interrupt Mask Register in the SDRAM Controller is not read-only. Thus, writing to it modi-
fies the contents instead of having no effect.
Problem Fix/Workaround
None.
41.8.2
No wrap-around for SDRAM devices with two internal banks
In the case of SDRAM devices featuring two internal banks, when the physical address is higher
than the memory size, the SDRAM controller does not wrap around. It activates virtual bank
numbers three or four.
Problem Fix/Workaround
None.
41.8.3
No t_RC after refresh when low-power mode is enabled
When low-power mode is enabled and after a refresh command is sent to the SDRAM, the
SDRAM Controller enters low-power mode by asserting SDCKE low. The t_RC timing between
Auto-refresh and Low-power mode is not respected. As SDCKE is low, the INHIBIT and NOP
commands are not sent to the SDRAM.
For the moment this warning has no effect on the correct functionality of the SDRAM.
Problem Fix/Workaround
None.
41.8.4
Some devices are not supported
The SDRAM controller does not support the following devices in 32-bit mode:
• 128 Mbit device: 32M*4bits: 4 banks/12 rows/11 columns
• 256 Mbit device: 64M*4bits: 4 banks/13 rows/11 columns
Problem Fix/Workaround
None.
41.8.5
Interrupt Disable Register
Writing 0 to the Interrupt Enable Register or to the Interrupt Disable Register modifies the value
of Interrupt Mask Register.
Problem Fix/Workaround
None.
41.9 SMC
41.9.1
Address Bus continuously active
The address bus is continuously driven with the address of the current access, even if it is an
internal one.
Problem Fix/Workaround
676 AT91RM9200
1768I–ATARM–09-Jul-09