AT91RM9200_09 Datasheet, PDF (384/701 Pages) ATMEL Corporation – ARM920T-based Microcontroller

28.6.2 SPI Mode Register
Name:
SPI_MR
Access Type:
Read/Write
31
30
29
23
22
21
–
–
–
15
14
13
–
–
–
7
6
5
LLB
–
–
28
27
DLYBCS
20
19
–
12
11
–
–
4
MODFDIS
3
DIV32
26
25
18
17
PCS
10
9
–
–
2
1
PCSDEC
PS
24
16
8
–
0
MSTR
• MSTR: Master/Slave Mode
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
• PS: Peripheral Select
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
• PCSDEC: Chip Select Decode
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 16 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder.
The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules:
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 15*.
*Note: The 16th state corresponds to a state in which all chip selects are inactive. This allows a different clock configuration
to be defined by each chip select register.
• DIV32: Clock Selection
0 = The SPI operates at MCK.
1 = The SPI operates at MCK/32.
• MODFDIS: Mode Fault Detection
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
• LLB: Local Loopback Enable
384 AT91RM9200
1768I–ATARM–09-Jul-09