AT91RM9200_09 Datasheet, PDF (605/701 Pages) ATMEL Corporation – ARM920T-based Microcontroller

AT91RM9200
36.5.1 Media Independent Interface
36.5.1.1
General
The Ethernet MAC is capable of interfacing to both RMII and MII Interfaces. The RMII bit in the
ETH_CFG register controls the interface that is selected. When this bit is set, the RMII interface
is selected, else the MII interface is selected.
The MII and RMII interface are capable of both 10Mb/s and 100Mb/s data rates as described in
the IEEE 802.3u standard. The signals used by the MII and RMII interfaces are described in the
Table 36-1.
Table 36-1. Pin Configurations
Pin Name
MII
ETXCK_REFCK ETXCK: Transmit Clock
ECRS_ECRSDV ECRS: Carrier Sense
ECOL
ECOL: Collision Detect
ERXDV
ERXDV: Data Valid
ERX0 - ERX3
ERX0 - ERX3: 4-bit Receive Data
ERXER
ERXER: Receive Error
ERXCK
ERXCK: Receive Clock
ETXEN
ETXEN: Transmit Enable
ETX0-ETX3
ETX0 - ETX3: 4-bit Transmit Data
ETXER
ETXER: Transmit Error
RMII
REFCK: Reference Clock
ECRSDV: Carrier Sense/Data Valid
ERX0 - ERX1: 2-bit Receive Data
ERXER: Receive Error
ETXEN: Transmit Enable
ETX0 - ETX1: 2-bit Transmit Data
The intent of the RMII is to provide a reduced pin count alternative to the IEEE 802.3u MII. It
uses 2 bits for transmit (ETX0 and ETX1) and two bits for receive (ERX0 and ERX1). There is a
Transmit Enable (ETXEN), a Receive Error (ERXER), a Carrier Sense (ECRS_DV), and a 50
MHz Reference Clock (ETXCK_REFCK) for 100Mb/s data rate.
36.5.1.2
RMII Transmit and Receive Operation
The same signals are used internally for both the RMII and the MII operations. The RMII maps
these signals in a more pin-efficient manner. The transmit and receive bits are converted from a
4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. The carrier sense
and data valid signals are combined into the ECRS_ECRSDV signal. This signal contains infor-
mation on carrier sense, FIFO status, and validity of the data. Transmit error bit (ETXER) and
collision detect (ECOL) are not used in RMII mode.
36.5.2
Transmit/Receive Operation
A standard IEEE 802.3 packet consists of the following fields: preamble, start of frame delimiter
(SFD), destination address (DA), source address (SA), length, data (Logical Link Control Data)
and frame check sequence CRC32 (FCS).
Table 36-2. Packet Format
Preamble
Frame⁽¹⁾
Alternating 1s/0s
SFD
DA
SA
Length/type LLC Data PAD FCS
Up to 7 bytes
1 byte 6 bytes 6 bytes
2 bytes
4 bytes
1768I–ATARM–09-Jul-09
605