AT91RM9200_09 Datasheet, PDF (15/701 Pages) ATMEL Corporation – ARM920T-based Microcontroller

AT91RM9200
• Debug Unit
– Two-pin UART
– Debug Communication Channel
– Chip ID Register
• Embedded Trace Macrocell: ETM9^™ Rev2a
– Medium Level Implementation
– Half-rate Clock Mode
– Four Pairs of Address Comparators
– Two Data Comparators
– Eight Memory Map Decoder Inputs
– Two Counters
– One Sequencer
– One 18-byte FIFO
• IEEE1149.1 JTAG Boundary Scan on all Digital Pins
7.3 Boot Program
• Default Boot Program stored in ROM-based products
• Downloads and runs an application from external storage media into internal SRAM
• Downloaded code size depends on embedded SRAM size
• Automatic detection of valid application
• Bootloader supporting a wide range of non-volatile memories
– SPI DataFlash^® connected on SPI NPCS0
– Two-wire EEPROM
– 8-bit parallel memories on NCS0
• Boot Uploader in case no valid program is detected in external NVM and supporting several
communication media
• Serial communication on a DBGU (XModem protocol)
• USB Device Port (DFU Protocol)
7.4 Embedded Software Services
• Compliant with ATPCS
• Compliant with AINSI/ISO Standard C
• Compiled in ARM/Thumb Interworking
• ROM Entry Service
• Tempo, Xmodem and DataFlash services
• CRC and Sine tables
7.5 Memory Controller
• Programmable Bus Arbiter handling four Masters
– Internal Bus is shared by ARM920T, PDC, USB Host Port and Ethernet MAC
Masters
– Each Master can be assigned a priority between 0 and 7
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1768I–ATARM–09-Jul-09