SAM4N_14 Datasheet, PDF (590/795 Pages) ATMEL Corporation – ARM-based Flash MCU

32.8.7 USART Interrupt Disable Register
Name:
US_IDR
Address: 0x4002400C (0), 0x4002800C (1), 0x4002C00C (2)
Access:
Write-only
31
30
29
28
27
26
25
–
–
–
–
–
–
–
23
22
21
20
19
18
17
–
–
–
–
CTSIC
–
–
15
14
13
12
11
10
9
–
–
NACK
RXBUFF
TXBUFE
ITER
TXEMPTY
7
PARE
6
FRAME
5
OVRE
4
ENDTX
3
ENDRX
2
RXBRK
1
TXRDY
For SPI specific configuration, see “USART Interrupt Disable Register (SPI_MODE)” on page 591.
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• RXBRK: Receiver Break Interrupt Disable
• ENDRX: End of Receive Transfer Interrupt Disable (available in all USART modes of operation)
• ENDTX: End of Transmit Interrupt Disable (available in all USART modes of operation)
• OVRE: Overrun Error Interrupt Enable
• FRAME: Framing Error Interrupt Disable
• PARE: Parity Error Interrupt Disable
• TIMEOUT: Time-out Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• ITER: Max Number of Repetitions Reached Interrupt Disable
• TXBUFE: Buffer Empty Interrupt Disable (available in all USART modes of operation)
• RXBUFF: Buffer Full Interrupt Disable (available in all USART modes of operation)
• NACK: Non AcknowledgeInterrupt Disable
• CTSIC: Clear to Send Input Change Interrupt Disable
0: No effect
1: Disables the corresponding interrupt.
24
–
16
–
8
TIMEOUT
0
RXRDY
SAM4N Series [DATASHEET]
11158A–ATARM–07-Jun-13
590