SAM4N_14 Datasheet, PDF (295/795 Pages) ATMEL Corporation – ARM-based Flash MCU

Waking up the core power supply when a supply monitor detection occurs can be enabled by programming the SMEN bit
to 1 in the Supply Controller Wake-up Mode Register (SUPC_WUMR).
The Supply Controller provides two status bits in the Supply Controller Status Register for the supply monitor which
allows to determine whether the last wake-up was due to the supply monitor:
z The SMOS bit provides real time information, which is updated at each measurement cycle or updated at each
Slow Clock cycle, if the measurement is continuous.
z The SMS bit provides saved information and shows a supply monitor detection has occurred since the last read of
SUPC_SR.
The SMS bit can generate an interrupt if the SMIEN bit is set to 1 in the Supply Controller Supply Monitor Mode Register
(SUPC_SMMR).
Figure 19-2. Supply Monitor Status Bit and Associated Interrupt
Supply Monitor ON
Continuous Sampling (SMSMPL = 1)
Periodic Sampling
3.3 V
Threshold
0V
SMS and SUPC interrupt
Read SUPC_SR
19.4.5 Backup Power Supply Reset
19.4.5.1 Raising the Backup Power Supply
As soon as the backup voltage VDDIO rises, the RC oscillator is powered up and the zero-power power-on reset cell
maintains its output low as long as VDDIO has not reached its target voltage. During this time, the Supply Controller is
entirely reset. When the VDDIO voltage becomes valid and zero-power power-on reset signal is released, a counter is
started for 5 slow clock cycles. This is the time it takes for the 32 kHz RC oscillator to stabilize.
After this time,the voltage regulator is enabled. The core power supply rises and the brownout detector provides the
bodcore_in signal as soon as the core voltage VDDCORE is valid. This results in releasing the vddcore_nreset signal to
the Reset Controller after the bodcore_in signal has been confirmed as being valid for at least one slow clock cycle.
SAM4N Series [DATASHEET]
11158A–ATARM–07-Jun-13
295