SAM4N_14 Datasheet, PDF (381/795 Pages) ATMEL Corporation – ARM-based Flash MCU

Oscillator is disabled when a clock failure detection occurs, it is automatically re-enabled by the clock failure detection
mechanism.
It takes 2 slow clock RC oscillator cycles to detect and switch from the 3 to 20 MHz Crystal, or Ceramic Resonator-based
Oscillator, to the 12/8/4 MHz Fast RC Oscillator if the Master Clock source is Main Clock, or 3 slow clock RC oscillator
cycles if the Master Clock source is PLLACK .
A clock failure detection activates a fault output that is connected to the Pulse Width Modulator (PWM) Controller. With
this connection, the PWM controller is able to force its outputs and to protect the driven device, if a clock failure is
detected. This fault output remains active until the defect is detected and until it is cleared by the bit FOCLR in the PMC
Fault Output Clear Register (PMC_FOCR).
The user can know the status of the fault output at any time by reading the FOS bit in the PMC_SR register.
26.2.12 Slow Crystal Clock Frequency Monitor
The frequency of the slow clock crystal oscillator can be monitored by means of logic driven by the main RC oscillator
known as a reliable clock source. This function is enabled by configuring the XT32KFME bit of the Main Oscillator
Register (CKGR_MOR).
An error flag (XT32KERR in PMC_SR) is asserted when the slow clock crystal oscillator frequency is out of the +/- 10%
nominal frequency value (i.e. 32768 kHz). The error flag can be cleared only if the slow clock frequency monitoring is
disabled.
When the main RC oscillator frequency is 4 MHz, the accuracy of the measurement is +/-40% as this frequency is not
trimmed during production. Therefore, +/-10% accuracy is obtained only if the RC oscillator frequency is configured for 8
or 12 MHz.
The monitored clock frequency is declared invalid if at least 4 consecutive clock period measurement results are over the
nominal period +/-10%.
Due to the possible frequency variation of the embedded main RC oscillator acting as reference clock for the monitor
logic, any slow clock crystal frequency deviation over +/-10% of the nominal frequency is systematically reported as an
error by means of XT32KERR in PMC_SR. Between -1% and -10% and +1% and +10%, the error is not systematically
reported.
Thus only a crystal running at 32768 kHz frequency ensures that the error flag will not be asserted. The permitted drift of
the crystal is 10000ppm (1%), which allows any standard crystal to be used.
If the main RC frequency needs to be changed while the slow clock frequency monitor is operating, the monitoring must
be stopped prior to change the main RC frequency. Then it can be re-enabled as soon as MOSCRCS is set in PMC_SR
register.
The error flag can be defined as an interrupt source of the PMC by setting the XT32KERR bit of PMC_IER.
26.2.13 Programming Sequence
1. Enabling the Main Oscillator:
The main oscillator is enabled by setting the MOSCXTEN field in the Main Oscillator Register (CKGR_MOR). The
user can define a start-up time. This can be achieved by writing a value in the MOSCXTST field in CKGR_MOR.
Once this register has been correctly configured, the user must wait for MOSCXTS field in the PMC_SR register to
be set. This can be done either by polling the status register, or by waiting the interrupt line to be raised if the asso-
ciated interrupt to MOSCXTS has been enabled in the PMC_IER register.
Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
The main oscillator will be enabled (MOSCXTS bit set) after 56 Slow Clock Cycles.
2. Checking the Main Oscillator Frequency (Optional):
In some situations the user may need an accurate measure of the main clock frequency. This measure can be
accomplished via the Main Clock Frequency Register (CKGR_MCFR).
SAM4N Series [DATASHEET]
11158A–ATARM–07-Jun-13
381