SAM4N_14 Datasheet, PDF (314/795 Pages) ATMEL Corporation – ARM-based Flash MCU

z One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is
write-only and accessible all along the 1 MByte address space, so that each word can be written to its final
address.
z Several lock bits used to protect write/erase operation on several pages (lock region). A lock bit is associated with
a lock region composed of several pages in the memory plane.
z Several bits that may be set and cleared through the Enhanced Embedded Flash Controller (EEFC) interface,
called General Purpose Non Volatile Memory bits (GPNVM bits).
The embedded Flash size, the page size, the lock regions organization and GPNVM bits definition are specific to the
product. The Enhanced Embedded Flash Controller (EEFC) returns a descriptor of the Flash controlled after a get
descriptor command issued by the application (see “Getting Embedded Flash Descriptor” on page 319).
Figure 21-1. Embedded Flash Organization
Start Address
Memory Plane
Page 0
Page (m-1)
Lock Region 0
Lock Bit 0
Lock Region 1
Lock Bit 1
Start Address + Flash size -1
Page (n*m-1)
Lock Region (n-1)
Lock Bit (n-1)
21.4.2 Read Operations
An optimized controller manages embedded Flash reads, thus increasing performance when the processor is running in
Thumb2 mode by means of the 128- or 64- bit wide memory interface.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash
wraps around the address space and appears to be repeated within it.
The read operations can be performed with or without wait states. Wait states must be programmed in the field FWS
(Flash Read Wait State) in the Flash Mode Register (EEFC_FMR). Defining FWS to be 0 enables the single-cycle
access of the embedded Flash. Refer to the Electrical Characteristics for more details.
21.4.2.1 128-bit or 64-bit Access Mode
By default the read accesses of the Flash are performed through a 128-bit wide memory interface. It enables better
system performance especially when 2 or 3 wait state needed.
For systems requiring only 1 wait state, or to privilege current consumption rather than performance, the user can select
a 64-bit wide memory access via the FAM bit in the Flash Mode Register (EEFC_FMR)
Please refer to the electrical characteristics section of the product datasheet for more details.
SAM4N Series [DATASHEET]
11158A–ATARM–07-Jun-13
314