SAM4N_14 Datasheet, PDF (182/795 Pages) ATMEL Corporation – ARM-based Flash MCU

13.8.3.1 Interrupt Set-enable Registers
Name:
NVIC_ISERx [x=0..7]
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
SETENA
23
22
21
20
19
18
17
16
SETENA
15
14
13
12
11
10
9
8
SETENA
7
6
5
4
3
2
1
0
SETENA
These registers enable interrupts and show which interrupts are enabled.
• SETENA: Interrupt Set-enable
Write:
0: No effect.
1: Enables the interrupt.
Read:
0: Interrupt disabled.
1: Interrupt enabled.
Notes: 1. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority.
2. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, the NVIC never acti-
vates the interrupt, regardless of its priority.
SAM4N Series [DATASHEET]
11158A–ATARM–07-Jun-13
182