SAM4N_14 Datasheet, PDF (575/795 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 32-29.SPI Transfer Format (CPHA=0, 8 bits per transfer)
SCK cycle (for reference)
1
2
3
4
5
6
7
8
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MOSI
SPI Master ->TXD
SPI Slave ->RXD
MISO
SPI Master ->RXD
SPI Slave ->TXD
NSS
SPI Master ->RTS
SPI Slave ->CTS
MSB
6
5
4
3
2
1
LSB
MSB
6
5
4
3
2
1
LSB
32.7.7.4 Receiver and Transmitter Control
See “Receiver and Transmitter Control” on page 558.
32.7.7.5 Character Transmission
The characters are sent by writing in the Transmit Holding Register (US_THR). An additional condition for transmitting a
character can be added when the USART is configured in SPI master mode. In the USART_MR register, the value
configured on INACK field can prevent any character transmission (even if US_THR has been written) while the receiver
side is not ready (character not read). When WRDBT equals 0, the character is transmitted whatever the receiver status.
If WRDBT is set to 1, the transmitter waits for the receiver holding register to be read before transmitting the character
(RXRDY flag cleared), thus preventing any overflow (character loss) on the receiver side.
The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which
indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been
processed. When the current character processing is completed, the last character written in US_THR is transferred into
the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY
is low has no effect and the written character is lost.
If the USART is in SPI Slave Mode and if a character must be sent while the Transmit Holding Register (US_THR) is
empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE
bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
In SPI Master Mode, the slave select line (NSS) is asserted at low level 1 Tbit (Time bit) before the transmission of the
MSB bit and released at high level 1 Tbit after the transmission of the LSB bit. So, the slave select line (NSS) is always
released between each character transmission and a minimum delay of 3 Tbits always inserted. However, in order to
address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line (NSS) can
be forced at low level by writing the Control Register (US_CR) with the RTSEN bit to 1. The slave select line (NSS) can
be released at high level only by writing the Control Register (US_CR) with the RTSDIS bit to 1 (for example, when all
data have been transferred to the slave device).
SAM4N Series [DATASHEET]
11158A–ATARM–07-Jun-13
575