AT91SAM9G45B-CU Datasheet, PDF (585/1185 Pages) ATMEL Corporation – AT91SAM ARM-based Embedded MPU

33.7.8.7 Slave Node Synchronization
The synchronization is done only in Slave node configuration. The procedure is based on time measurement
between falling edges of the Synch Field. The falling edges are available in distances of 2, 4, 6 and 8 bit times.
Figure 33-42. Synch Field
Synch Field
8 Tbit
2 Tbit
Start
bit
2 Tbit
2 Tbit
2 Tbit
Stop
bit
The time measurement is made by a 19-bit counter clocked by the sampling clock (see Section 33.7.1).
When the start bit of the Synch Field is detected the counter is reset. Then during the next 8 Tbits of the Synch
Field, the counter is incremented. At the end of these 8 Tbits, the counter is stopped. At this moment, the 16 most
significant bits of the counter (value divided by 8) gives the new clock divider (CD) and the 3 least significant bits of
this value (the remainder) gives the new fractional part (FP).
When the Synch Field has been received, the clock divider (CD) and the fractional part (FP) are updated in the
Baud Rate Generator register (US_BRGR).
Figure 33-43. Slave Node Synchronization
Baud Rate
Clock
RXD
LINIDRX
Break Field
13 dominant bits (at 0)
Synchro Counter
Break
Delimiter
1 recessive bit
Start
Bit
1
01010
Synch Byte = 0x55
1
0
Stop Start
Bit Bit
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
Stop
Bit
(at 1)
Reset
000_0011_0001_0110_1101
US_BRGR
Clcok Divider (CD)
US_BRGR
Fractional Part (FP)
Initial CD
Initial FP
0000_0110_0010_1101
101
The accuracy of the synchronization depends on several parameters:
• The nominal clock frequency (F_Nom) (the theoretical slave node clock frequency)
• The Baudrate
• The oversampling (Over=0 => 16X or Over=0 => 8X)
SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
585