AT91SAM9G45B-CU Datasheet, PDF (1061/1185 Pages) ATMEL Corporation – AT91SAM ARM-based Embedded MPU

Table 45-9. Palette Configurations (Continued)
Configuration
DISTYPE
PIXELSIZE
STN Mono
4
STN Color
1, 2, 4, 8
STN Color
16
Palette
Non-palletized
Palletized
Non-palletized
The lookup table can be accessed by the host in R/W mode to allow the host to program and check the values
stored in the palette. It is mapped in the LCD controller configuration memory map. The LUT is mapped as 16-bit
half-words aligned at word boundaries, only word write access is allowed (the 16 MSB of the bus are not used). For
the detailed memory map, see Table 45-16 on page 1079.
The lookup table contains 256 16-bit wide entries. The 256 entries are chosen by the programmer from the 2¹⁶
possible combinations.
For the structure of each LUT entry, see Table 45-10.
Table 45-10. Lookup Table Structure in the Memory
Address
Data Output [15:0]
00
Red_value_0[4:0]
Green_value_0[5:0]
01
Red_value_1[4:0]
Green_value_1[5:0]
...
FE
Red_value_254[4:0]
Green_value_254[5:0]
FF
Red_value_255[4:0]
Green_value_255[5:0]
Blue_value_0[4:0]
Blue_value_1[4:0]
Blue_value_254[4:0]
Blue_value_255[4:0]
In STN Monochrome, only the four most significant bits of the red value are used (16 gray shades). In STN Color,
only the four most significant bits of the blue, green and red value are used (4096 colors).
In TFT mode, all the bits in the blue, green and red values are used. The LCDD unused bits are tied to 0 when TFT
palletized configurations are used (LCDD[18:16], LCDD[9:8], LCDD[2:0]).
45.6.2.6 Dithering
The dithering block is used to generate the shades of gray or color when the LCD Controller is used with an STN
LCD Module. It uses a time-based dithering algorithm and Frame Rate Control method.
The Frame Rate Control varies the duty cycle for which a given pixel is turned on, giving the display an appearance
of multiple shades. In order to reduce the flicker noise caused by turning on and off adjacent pixels at the same
time, a time-based dithering algorithm is used to vary the pattern of adjacent pixels every frame. This algorithm is
expressed in terms of Dithering Pattern registers (DP_i) and considers not only the pixel gray level number, but
also its horizontal coordinate.
Table 45-11 shows the correspondences between the gray levels and the duty cycle.
Table 45-11. Dithering Duty Cycle
Gray Level
Duty Cycle
15
1
14
6/7
13
4/5
12
3/4
Pattern Register
-
DP6_7
DP4_5
DP3_4
SAM9G45 [DATASHEET] 1061
6438K–ATARM–12-Feb-13