AT91SAM9G45B-CU Datasheet, PDF (1139/1185 Pages) ATMEL Corporation – AT91SAM ARM-based Embedded MPU

46.15.5 EMAC
46.15.5.1 Timing Conditions
Timings are given assuming a capacitance load on data and clock:
Table 46-41. Capacitance Load on Data, Clock Pads
Corner
Supply
MAX
MIN
3.3V
20pF
0pF
1.8V
20pF
0pF
46.15.5.2 Timing Constraints
The Ethernet controller must satisfy the timings of MAX corner standards given in Table 46-42 and Table 46-43.
Table 46-42. EMAC Signals Relative to EMDC
Symbol
Parameter
EMAC₁
EMAC₂
EMAC₃
Setup for EMDIO from EMDC rising
Hold for EMDIO from EMDC rising
EMDIO toggling from EMDC falling
Min (ns)
13.5
10
0 ⁽¹⁾
Max (ns)
2 ⁽¹⁾
Notes: 1. For EMAC output signals, Min and Max access time are defined. The Min access time is the time between the EDMC falling
edge and the signal change. The Max access time is the time between the EDMC falling edge and the signal stabilization.
Figure 46-20 illustrates Min and Max accesses for EMAC3.
Figure 46-20. Min and Max Access Time of EMAC Output Signals
EMDC
EMDIO
EMAC₁
EMAC₂
EMAC₄
EMAC₅
EMAC_{3 max}
EMAC_{3 min}
46.15.5.3 MII Mode
Table 46-43. EMAC MII Specific Signals
Symbol
Parameter
EMAC₄
EMAC₅
EMAC₆
EMAC₇
EMAC₈
EMAC₉
Setup for ECOL from ETXCK rising
Hold for ECOL from ETXCK rising
Setup for ECRS from ETXCK rising
Hold for ECRS from ETXCK rising
ETXER toggling from ETXCK rising
ETXEN toggling from ETXCK rising
Min (ns)
10
10
10
10
3
4.7
Max (ns)
25
25
SAM9G45 [DATASHEET] 1139
6438K–ATARM–12-Feb-13