AT91SAM9G45B-CU Datasheet, PDF (18/1185 Pages) ATMEL Corporation – AT91SAM ARM-based Embedded MPU

6.3 I/O Drive Selection and Delay Control
6.3.1
I/O Drive Selection
The aim of this control is to adapt the signal drive to the frequency. Two bits allow the user to select High or Low
drive for memories data/address/ctrl signals.
• Setting the bit [17], EBI_DRIVE, in the EBI_CSA register of the matrix allows to control the drive of the EBI.
• Setting the bit [18], DDR_DRIVE, in the EBI_CSA register of the matrix allows to control the drive of the DDR.
6.3.2
Delay Control
To avoid the simultaneous switching of all the I/Os, a delay can be inserted on the different EBI, DDR2 and PIO
lines.
The control of these delays is the following:
• DDRSDRC
DDR_D[15:0] controlled by 2 registers, DELAY1 and DELAY2, located in the DDRSDRC user interface
– DDR_D[0] <=> DELAY1[3:0],
– DDR_D[1] <=> DELAY1[7:4],...
– DDR_D[6] <=> DELAY1[27:24],
– DDR_D[7] <=> DELAY1[31:28]
– DDR_D[8] <=> DELAY2[3:0],
– DDR_D[9] <=> DELAY2[7:4],...,
– DDR_D[14] <=> DELAY2[27:24],
– DDR_D[15] <=> DELAY2[31:28]
DDR_A[13:0] controlled by 2 registers, DELAY3 and DELAY4, located in the DDRSDRC user interface
– DDR_A[0] <=> DELAY3[3:0],
– DDR_A[1] <=> DELAY3[7:4], ...,
– DDR_A[6] <=> DELAY3[27:24],
– DDR_A[7] <=> DELAY3[31:28]
– DDR_A[8] <=> DELAY4[3:0],
– DDR_A[9] <=> DELAY4[7:4], ...,
– DDR_A[12] <=> DELAY4[19:16],
– DDR_A[13] <=> DELAY4[23:20]
• EBI (DDRSDRC\HSMC3\Nandflash)
D[15:0] controlled by 2 registers, DELAY1 and DELAY2, located in the HSMC3 user interface
– D[0] <=> DELAY1[3:0],
– D[1] <=> DELAY1[7:4],...,
– D[6] <=> DELAY1[27:24],
– D[7] <=> DELAY1[31:28]
– D[8] <=> DELAY2[3:0],
– D[9] <=> DELAY2[7:4],...,
– D[14] <=> DELAY2[27:24],
– D[15] <=> DELAY2[31:28]
SAM9G45 [DATASHEET] 18
6438K–ATARM–12-Feb-13