AT91SAM9G45B-CU Datasheet, PDF (162/1185 Pages) ATMEL Corporation – AT91SAM ARM-based Embedded MPU

20.2.5 Application Example
20.2.5.1 Hardware Interface
Table 20-4 on page 162 details the connections to be applied between the EBI pins and the external devices for
each Memory Controller.
Table 20-4. EBI Pins and External Static Devices Connections
Pins of the Interfaced Device
Signals:
EBI_
8-bit Static
Device
2 x 8-bit
Static
Devices
16-bit Static
Device
4 x 8-bit
Static
Devices
Controller
SMC
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D8 - D15
–
D8 - D15
D8 - D15
D8 - D15
D16 - D23
–
–
–
D16 - D23
D24 - D31
–
–
–
D24 - D31
A0/NBS0
A0
A1/NWR2/NBS2
A1
–
NLB
–
A0
A0
WE⁽²⁾
A2 - A22
A23 - A25⁽⁵⁾
A[2:22]
A[23:25]
A[1:21]
A[22:24]
A[1:21]
A[22:24]
A[0:20]
A[21:23]
NCS0
CS
CS
CS
CS
NCS1/DDRSDCS
CS
CS
CS
CS
NCS2
CS
CS
CS
CS
NCS3/NANDCS
CS
CS
CS
CS
NCS4/CFCS0
CS
CS
CS
CS
NCS5/CFCS1
CS
CS
CS
CS
NRD/CFOE
OE
OE
OE
OE
NWR0/NWE
WE
WE⁽¹⁾
WE
WE⁽²⁾
NWR1/NBS1
–
WE⁽¹⁾
NUB
WE⁽²⁾
NWR3/NBS3
–
–
–
WE⁽²⁾
Notes: 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes.
1. NWRx enables corresponding byte x writes. (x = 0,1,2 or 3)
2. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.
3. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.
2 x 16-bit
Static
Devices
D0 - D7
D8 - 15
D16 - D23
D24 - D31
NLB⁽³⁾
NLB⁽⁴⁾
A[0:20]
A[21:23]
CS
CS
CS
CS
CS
CS
OE
WE
NUB⁽³⁾
NUB⁽⁴⁾
32-bit Static
Device
D0 - D7
D8 - 15
D16 - D23
D24 - D31
BE0
BE2
A[0:20]
A[21:23]
CS
CS
CS
CS
CS
CS
OE
WE
BE1
BE3
SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
162