AT91SAM9G45B-CU Datasheet, PDF (1124/1185 Pages) ATMEL Corporation – AT91SAM ARM-based Embedded MPU

– T1 = 66 μs
– T2 = 352 μs
As a conclusion, establish VDDIOP and VDDIOM first, and VDDCORE at last to ensure a reliable operation of the
device. VDDOSC, VDDPLL, VDDUTMII and VDDUTMIC must be stated at any time but before VDDCORE to
ensure a correct behaviour of the ROM code.
46.13 SMC Timings
46.13.1 Timing Conditions
SMC Timings are given for MAX corners.
Timings are given assuming a capacitance load on data, control and address pads:
Table 46-26. Capacitance Load
Corner
Supply
MAX
MIN
3.3V
50pF
5 pF
1.8V
30 pF
5 pF
In the following tables, t_CPMCK is MCK period.
46.13.2 Timing Extraction
46.13.2.1 Zero Hold Mode Restrictions
Table 46-27. Zero Hold Mode Use Maximum system clock frequency (MCK)
Symbol
Parameter
Min
VDDIOM supply
1.8V
3.3V
Zero Hold Mode Use
Fmax
MCK frequency
66
66
46.13.2.2 Read Timings
Units
MHz
Table 46-28. SMC Read Signals - NRD Controlled (READ_MODE= 1)
Symbol Parameter
Min
VDDIOM supply
1.8V
NO HOLD SETTINGS (nrd hold = 0)
SMC₁
SMC₂
Data Setup before NRD High
Data Hold after NRD High
12.0
0
HOLD SETTINGS (nrd hold ≠ 0)
SMC₃
SMC₄
Data Setup before NRD High
8.7
Data Hold after NRD High
0
HOLD or NO HOLD SETTINGS (nrd hold ≠ 0, nrd hold =0)
3.3V
11.2
0
8.2
0
Units
ns
ns
ns
ns
SAM9G45 [DATASHEET] 1124
6438K–ATARM–12-Feb-13