AT91SAM7XC512_14 Datasheet, PDF (514/731 Pages) ATMEL Corporation – High-performance 32-bit RISC Architecture

36.5 Security Features
36.5.1
Unspecified Register Access Detection
When an unspecified register access occurs, the URAD bit in the Interrupt Status Register
(AES_ISR) raises. Its source is then reported in the Unspecified Register Access Type field
(URAT). Only the last unspecified register access is available through the URAT field.
Several kinds of unspecified register accesses can occur:
• Input Data Register written during the data processing when SMOD=IDATAR0_START
• Output Data Register read during data processing
• Mode Register written during data processing
• Output Data Register read during sub-keys generation
• Mode Register written during sub-keys generation
• Write-only register read access
The URAD bit and the URAT field can only be reset by the SWRST bit in the AES_CR control
register.
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