AT91SAM7XC512_14 Datasheet, PDF (275/731 Pages) ATMEL Corporation – High-performance 32-bit RISC Architecture

AT91SAM7XC512/256/128
28.7.6 SPI Interrupt Enable Register
Name:
SPI_IER
Access Type:
Write-only
31
30
29
–
–
–
23
22
21
–
–
–
15
14
13
–
–
–
7
TXBUFE
6
RXBUFF
5
ENDTX
28
–
20
–
12
–
4
ENDRX
27
–
19
–
11
–
3
OVRES
• RDRF: Receive Data Register Full Interrupt Enable
• TDRE: SPI Transmit Data Register Empty Interrupt Enable
• MODF: Mode Fault Error Interrupt Enable
• OVRES: Overrun Error Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
• TXEMPTY: Transmission Registers Empty Enable
• NSSR: NSS Rising Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
26
–
18
–
10
–
2
MODF
25
–
17
–
9
TXEMPTY
1
TDRE
24
–
16
–
8
NSSR
0
RDRF
6209H–ATARM–15-Apr-13
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