AT91SAM7XC512_14 Datasheet, PDF (423/731 Pages) ATMEL Corporation – High-performance 32-bit RISC Architecture

32.6.11 TC Interrupt Enable Register
Register Name:
TC_IERx [x=0..2]
Access Type:
Write-only
31
30
29
–
–
–
23
22
21
–
–
–
15
14
13
–
–
–
7
ETRGS
6
LDRBS
5
LDRAS
• COVFS: Counter Overflow
0 = No effect.
1 = Enables the Counter Overflow Interrupt.
• LOVRS: Load Overrun
0 = No effect.
1 = Enables the Load Overrun Interrupt.
• CPAS: RA Compare
0 = No effect.
1 = Enables the RA Compare Interrupt.
• CPBS: RB Compare
0 = No effect.
1 = Enables the RB Compare Interrupt.
• CPCS: RC Compare
0 = No effect.
1 = Enables the RC Compare Interrupt.
• LDRAS: RA Loading
0 = No effect.
1 = Enables the RA Load Interrupt.
• LDRBS: RB Loading
0 = No effect.
1 = Enables the RB Load Interrupt.
• ETRGS: External Trigger
0 = No effect.
1 = Enables the External Trigger Interrupt.
28
–
20
–
12
–
4
CPCS
AT91SAM7XC512/256/128
27
–
19
–
11
–
3
CPBS
26
–
18
–
10
–
2
CPAS
25
–
17
–
9
–
1
LOVRS
24
–
16
–
8
–
0
COVFS
6209H–ATARM–15-Apr-13
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