AT91SAM7XC512_14 Datasheet, PDF (326/731 Pages) ATMEL Corporation – High-performance 32-bit RISC Architecture

• FSOS: Receive Frame Sync Output Selection
FSOS
Selected Receive Frame Sync Signal
0x0
None
0x1
Negative Pulse
0x2
Positive Pulse
0x3
Driven Low during data transfer
0x4
Driven High during data transfer
0x5
Toggling at each start of data transfer
0x6-0x7
Reserved
RF Pin
Input-only
Output
Output
Output
Output
Output
Undefined
• FSEDGE: Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
FSEDGE
0x0
0x1
Frame Sync Edge Detection
Positive Edge Detection
Negative Edge Detection
326 AT91SAM7XC512/256/128
6209H–ATARM–15-Apr-13