T5557 Datasheet, PDF (5/30 Pages) ATMEL Corporation – Multifunctional 330-bit Read/Write RF-Identification IC

T5557
Traceability Data
Structure
Blocks 1 and 2 of page 1 contain the traceability data and are programmed and locked
by Atmel during production testing. The most significant byte of block 1 is fixed to
‘E0’hex, the allocation class (ACL) as defined in ISO/IEC 15963-1. The second byte is
therefore defined as the manufacturer’s ID of Atmel (= ‘15’hex). The following 8 bits are
used as IC reference byte (ICR - Bits 47 to 40). The 3 most significant bits define the IC
and/or foundry version of the T5557. The lower 5 bits are by default reset (=00) as the
Atmel standard value. Other values may be assigned on request to high volume custom-
ers as tag issuer identification.
The lower 40 bits of the data encode the traceability information of Atmel and conform to
a unique numbering system. These 40 data bits are divided in two sub-groups, a 5-digit
lot ID number, the binary wafer number (5 bit) concatenated with the sequential die
number per wafer.
Figure 5. T5557 Traceability Data Structure
12
' 557 '
Traceability
20
Block 2
Block 1
1
...
12 13 ... 18 19
...
31 32
LotID
wafer #
die on wafer #
ACL
MFC
ICR
MSN LotID
1 ... 8 9 ... 16 17 ... 24 25 ... 32
Example:
' E0 '
' 15 '
' 00 '
' 41 '
8
ACL
MFC
ICR
MSN
LotID
DPW
Allocation class as defined in ISO/IEC 15963-1 = E0h
Manufacturer code of Atmel Corporation as defined in ISO/IEC 7816-6 = 15h
IC reference of silicon and/or tag manufacturer
Top 3 bits define IC revision
Lower 5 bits may contain a customer ID code on request
Manufacturer serial number consists of:
5-digit lot number, e.g., ’38765’
20 bits encoded as sequential die per wafer number (with top 5 bits = wafer#)
Operating the T5557
Initialization and
POR Delay
The Power-On-Reset (POR) circuit remains active until an adequate voltage threshold
has been reached. This in turn triggers the default start-up delay sequence. During this
configuration period of about 192 field clocks, the T5557 is initialized with the configura-
tion data stored in EEPROM block 0. During initialization of the configuration block 0, all
T55570x variants the load damping is active permanently (see Figure 10). The T55571x
types (without damping option) achieve a longer read range based on the lower activa-
tion field strength.
If the POR-delay bit is reset, no additional delay is observed after the configuration
period. Tag modulation in regular-read mode will be observed about 3 ms after entering
the RF field. If the POR delay bit is set, the T5557 remains in a permanent damping
state until 8190 internal field clocks have elapsed.
T_INIT = (192 + 8190 ´ POR delay) ´ T_C » 67 ms ; T_C = 8 µs at 125 kHz
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4517E–RFID–02/03