T5557 Datasheet, PDF (3/30 Pages) ATMEL Corporation – Multifunctional 330-bit Read/Write RF-Identification IC

T5557
Power-On Reset (POR)
Clock Extraction
Controller
Mode Register
This circuit delays the IDIC functionality until an acceptable voltage threshold has been
reached.
The clock extraction circuit uses the external RF signal as its internal clock source.
The control-logic module executes the following functions:
• Load-mode register with configuration data from EEPROM block 0 after power-on
and also during reading
• Control memory access (read, write)
• Handle write data transmission and write error modes
• The first two bits of the reader to tag data stream are the opcode, e.g., write, direct
access or reset
• In password mode, the 32 bits received after the opcode are compared with the
password stored in memory block 7
The mode register stores the configuration data from the EEPROM block 0. It is
continually refreshed at the start of every block read and (re-)loaded after any POR
event or reset command. On delivery the mode register is preprogrammed with the
value ‘0014 8000’h which corresponds to continuous read of block 0, Manchester
coded, RF/64.
Figure 3. Block 0 Configuration Mapping – e5550 Compatibility Mode
L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
01100000000
0
0
00
Safer Key
Data
Modulation PSK-
MAX-
Note 1), 2)
Bit Rate
CF
BLOCK
0 Unlocked
1 Locked
RF/8
RF/16
RF/32
RF/40
RF/50
000
001
010
011
100
0 0 RF/2
0 1 RF/4
1 0 RF/8
1 1 Res.
0 0 0 0 0 Direct
RF/64 1 0 1 0 0 0 0 1 PSK1
RF/100 1 1 0 0 0 0 1 0 PSK2
RF/128 1 1 1 0 0 0 1 1 PSK3
0 0 1 0 0 FSK1
0 0 1 0 1 FSK2
0 0 1 1 0 FSK1a
0 0 1 1 1 FSK2a
0 1 0 0 0 Manchester
1 0 0 0 0 Biphase('50)
1 1 0 0 0 Reserved
1) If Master Key = 6 then test mode write commands are ignored
2) If Master Key <> 6 or 9 then extended function mode is disabled
3
4517E–RFID–02/03