AT32UC3L064_1 Datasheet, PDF (492/825 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32UC3L
22.8.5.2
Data Receive with the Peripheral DMA Controller
1. Initialize the receive Peripheral DMA Controller (memory pointers, size, etc.).
2. Configure the TWIM (ADR, NBYTES, etc.).
3. Start the transfer by setting the Peripheral DMA Controller RXTEN bit.
4. Wait for the Peripheral DMA Controller end RX flag.
5. Disable the Peripheral DMA Controller by setting the Peripheral DMA Controller
RXDIS bit.
22.8.6
Multi-master Mode
More than one master may access the bus at the same time without data corruption by using
arbitration.
Arbitration starts as soon as two or more masters place information on the bus at the same
time, and stops (arbitration is lost) for the master that intends to send a logical one while the
other master sends a logical zero.
As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order
to detect a STOP. The SR.ARBLST flag will be set. When the STOP is detected, the master
who lost arbitration may reinitiate the data transfer.
Arbitration is illustrated in Figure 22-11 on page 493.
If the user starts a transfer and if the bus is busy, TWIM automatically waits for a STOP condi-
tion on the bus before initiating the transfer (see Figure 22-10 on page 492).
Note: The state of the bus (busy or free) is not indicated in the user interface.
Figure 22-10. Programmer Sends Data While the Bus is Busy
TWCK
TWD
TWI DATA transfer
STOP sent by the master
START sent by the TWI
DATA sent by a master
Bus is busy
Transfer is kept
Bus is free
DATA sent by the TWI
A transfer is programmed
(DADR + W + START + Write THR)
Bus is considered as free
Transfer is initiated
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