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AT32UC3L064_1 Datasheet, PDF (371/825 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller | |||
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AT32UC3L
20. Universal Synchronous Asynchronous Receiver Transmitter (USART)
Rev.4.4.0.3
20.1 Features
⢠Programmable Baud Rate Generator
⢠5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
â 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode
â Parity Generation and Error Detection
â Framing Error Detection, Overrun Error Detection
â MSB- or LSB-first
â Optional Break Generation and Detection
â By 8 or by 16 Over-sampling Receiver Frequency
â Optional Hardware Handshaking RTS-CTS
â Receiver Time-out and Transmitter Timeguard
â Optional Multidrop Mode with Address Generation and Detection
⢠SPI Mode
â Master or Slave
â Serial Clock Programmable Phase and Polarity
â SPI Serial Clock (CLK) Frequency up to Internal Clock Frequency CLK_USART/4
⢠LIN Mode
â Compliant with LIN 1.3 and LIN 2.0 specifications
â Master or Slave
â Processing of frames with up to 256 data bytes
â Response Data length can be configurable or defined automatically by the Identifier
â Self synchronization in Slave node configuration
â Automatic processing and verification of the âSynch Breakâ and the âSynch Fieldâ
â The âSynch Breakâ is detected even if it is partially superimposed with a data byte
â Automatic Identifier parity calculation/sending and verification
â Parity sending and verification can be disabled
â Automatic Checksum calculation/sending and verification
â Checksum sending and verification can be disabled
â Support both âClassicâ and âEnhancedâ checksum types
â Full LIN error checking and reporting
â Frame Slot Mode: the Master allocates slots to the scheduled frames automatically.
â Generation of the Wakeup signal
⢠Test Modes
â Remote Loopback, Local Loopback, Automatic Echo
⢠Supports Connection of Two Peripheral DMA Controller Channels (PDCA)
â Offers Buffer Transfer without Processor Intervention
20.2 Overview
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full
duplex universal synchronous asynchronous serial link. Data frame format is widely programma-
ble (data length, parity, number of stop bits) to support a maximum of standards. The receiver
implements parity error, framing error and overrun error detection. The receiver time-out enables
handling variable-length frames and the transmitter timeguard facilitates communications with
slow remote devices. Multidrop communications are also supported through address bit han-
dling in reception and transmission.
32099AâAVR32â06/09
371
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