AT32UC3L064_1 Datasheet, PDF (338/825 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32UC3L
19.6.2.8
19.6.2.9
The Interrupt Flag Register (IFR) can be read by software to determine which pin(s) caused the
interrupt. The interrupt flag must be manually cleared by writing a zero to the corresponding bit
in IFR.
GPIO interrupts will only be generated when CLK_GPIO is enabled.
Input Glitch Filter
Input glitch filters can be enabled on each GPIO pin. When the glitch filter is enabled, a glitch
with duration of less than 1 CLK_GPIO cycle is automatically rejected, while a pulse with dura-
tion of 2 CLK_GPIO cycles or more is accepted. For pulse durations between 1 and 2
CLK_GPIO cycles, the pulse may or may not be taken into account, depending on the precise
timing of its occurrence. Thus for a pulse to be guaranteed visible it must exceed 2 CLK_GPIO
cycles, whereas for a glitch to be reliably filtered out, its duration must not exceed 1 CLK_GPIO
cycle. The filter introduces 2 clock cycles latency.
The glitch filters are controlled by the Glitch Filter Enable Register (GFER). When a bit in GFER
is one, the glitch filter on the corresponding pin is enabled. The glitch filter affects only interrupt
inputs. Inputs to peripherals or the value read through PVR are not affected by the glitch filters.
Interrupt Timings
Figure 19-4 shows the timing for rising edge (or pin-change) interrupts when the glitch filter is
disabled. For the pulse to be registered, it must be sampled at the rising edge of the clock. In this
example, this is not the case for the first pulse. The second pulse is sampled on a rising edge
and will trigger an interrupt request.
Figure 19-4. Interrupt Timing with Glitch Filter Disabled
CLK_GPIO
Pin Level
IFR
Figure 19-5 shows the timing for rising edge (or pin-change) interrupts when the glitch filter is
enabled. For the pulse to be registered, it must be sampled on two subsequent rising edges. In
the example, the first pulse is rejected while the second pulse is accepted and causes an inter-
rupt request.
Figure 19-5. Interrupt Timing with Glitch Filter Enabled
CLK_GPIO
Pin Level
IFR
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