AT32UC3L064_1 Datasheet, PDF (336/825 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32UC3L
19.6.2 Advanced Operation
19.6.2.1
Peripheral I/O Pin Control
When a GPIO pin is assigned to a peripheral function, i.e. the corresponding bit in GPER is zero,
output and output enable is controlled by the selected peripheral pin. In addition the peripheral
may control some or all of the other GPIO pin functions listed in Table 19-1, if the peripheral sup-
ports those features. All pin features not controlled by the selected peripheral is controlled by the
GPIO.
Refer to the Module Configuration section for details regarding implemented GPIO pin functions
and to the Peripheral chapter for details regarding I/O pin function control.
Table 19-1. I/O Pin function Control
Function name
GPIO mode
Output
OVR
Output enable
ODER
Pull-up
PUER
Pull-down
PDER
Buskeeper
PUER&PDER
Drive strength
ODCRn
Slew rate
OSRRn
Open drain
ODMR
Schmitt trigger
STER
Peripheral mode
Peripheral
Peripheral
Peripheral if supported, else GPIO
Peripheral if supported, else GPIO
Peripheral if supported, else GPIO
Peripheral if supported, else GPIO
Peripheral if supported, else GPIO
Peripheral if supported, else GPIO
Peripheral if supported, else GPIO
19.6.2.2
19.6.2.3
Pull-up Resistor, Pull-down Resistor and Buskeeper Control
Pull-up, pull-down, and buskeeper can be configured for each GPIO pin. Pull-up allows the pin
and any connected net to be pulled up to VDD if the net is not driven. Pull-down pulls the net to
GND, while buskeeper keeps the current logic level if the net becomes undriven.
Pull-up and pull-down are useful for detecting if a pin is unconnected or if a mechanical button is
pressed, for various communication protocols and to keep unconnected pins from floating.
Pull-up can be enabled and disabled by writing a one and a zero respectively to the correspond-
ing bit in the Pull-up Enable Register (PUER). Pull-down can be enabled and disabled by writing
a one and a zero respectively to the corresponding bit in the Pull-down Enable Register (PDER).
To enable the buskeeper for a pin, the corresponding bit in PUER and PDER must be written to
one.
Output Pin Timings
Figure 19-3 shows the timing of the GPIO pin when writing to the Output Value Register (OVR).
The same timing applies when performing a ‘set’ or ‘clear’ access, i.e. writing to OVRS or
OVRC. The timing of PVR is also shown.
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