AT32UC3L064_1 Datasheet, PDF (458/825 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

Figure 21-8. Peripheral Deselection
CSAAT = 0 and CSNAAT = 0
TDRE
NPCS[0..3]
Write TDR
DLYBCT
A
A
DLYBCS
PCS = A
TDRE
NPCS[0..3]
Write TDR
DLYBCT
A
A
DLYBCS
PCS=A
TDRE
DLYBCT
NPCS[0..3]
A
B
DLYBCS
PCS = B
Write TDR
AT32UC3L
CSAAT = 1 and CSNAAT= 0 / 1
DLYBCT
A
A
A
DLYBCS
PCS = A
DLYBCT
A
A
A
DLYBCS
PCS = A
DLYBCT
A
B
DLYBCS
PCS = B
TDRE
CSAAT = 0 and CSNAAT = 0
DLYBCT
CSAAT = 0 and CSNAAT = 1
DLYBCT
NPCS[0..3]
A
A
PCS = A
Write TDR
A
A
DLYBCS
PCS = A
Figure 21-8 on page 458 shows different peripheral deselection cases and the effect of the
CSRn.CSAAT and CSRn.CSNAAT bits.
21.7.3.9
Mode fault detection
A mode fault is detected when the SPI is configured in master mode and a low level is driven by
an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be config-
ured in open drain through the I/O Controller, so that external pull up resistors are needed to
guarantee high level.
32099A–AVR32–06/09
458