NSD-2101 Datasheet, PDF (9/22 Pages) ams AG – Piezo Motor Driver ASIC for SQL-RV Series Reduced Voltage SQUIGGLE® RV and UTAF™ Motors

NSD-2101
Data Sheet - Detailed Description
7.3 Frequency Tracking
Based on the motor type, an initial drive signal period must be written to the NSD-2101. The period is specified in units of 0.04 µsec (based on
the nominal internal VCO frequency of 25 MHz). In the case of an SQL-RV-1.8 motor, the period may be 148 (94h) to generate a drive frequency
of ~168.9 kHz.
The NSD-2101 is able to then optimize the drive frequency by, on command, sweeping over a range of frequencies, centered at the specified
period, and settling on the frequency at which the best motor performance was detected. Alternatively, the NSD-2101 may be commanded to
incrementally step the frequency in the direction of increasing motor performance (changing the step direction when the performance drops).
In either case, the NSD-2101 adjusts the frequency by adjusting the VCO trimming, rather than the period count. This affords much higher
resolution than is possible by changing the period count.
Whether sweep mode or incremental (see ‘Control Register’ in Table 8 on page 10), the calibration does not start until a pulse count has been
loaded into registers 02h and 03h.
A sweep calibration is typically performed following a power-up. The sweep calibration offers the greatest range of frequencies. Incremental
calibration offers the best frequency resolution and can be performed periodically as the motor is being used.
7.4 I²C
The I²C interface is used to control the NSD-2101 and set the value of several registers. These registers will define the direction and duration of
the output driver signals, the duty cycle, phase shift and average voltage to the motor.
Start/Stop Condition: A HIGH to LOW transition on the SDA line while SCL is HIGH is the start condition for the bus. A LOW to HIGH
transition on the SDA line while SCL is HIGH is the stop condition.
Every byte put on the SDA line must be 8-bits long. Each byte must be followed by an acknowledge bit. Data is transferred with the most
significant bit (MSB) first.
Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The receiver must pull down the
SDA line during the acknowledge clock pulse.
The NSD-2101 is a slave device on the bus. There are two different access modes:
- Byte write
- Page write
The device can be addressed using 7-bit addressing. The first 6 bits are fixed. The last bit can be set via package pin.
Figure 7. 7-Bit Device Address
www.austriamicrosystems.com/NSD-2101
Revision 0.4
9 - 22