NSD-2101 Datasheet, PDF (12/22 Pages) ams AG – Piezo Motor Driver ASIC for SQL-RV Series Reduced Voltage SQUIGGLE® RV and UTAF™ Motors

NSD-2101
Data Sheet - Detailed Description
7.8 Pulse Counter
The pulse counter sets the number of pulses the motor should be active. When a new value is written to the pulse count register an internal
counter is started to count generated output pulses. Writing all zeros to the pulse counter stops the motor even if the previous set counter value
is not completed, all outputs pulled to ground. The same is valid for power down mode. Bit 6 in the pulse counter (d) is used to set the direction
of motor motion.
Table 11. Pulse Counter Values
Pulse Counter Value
Typ
Unit
Conditions
XXXX X000 0000 0000
0
pulses
Motor is off, driver outputs are low
XXXX X100 0000 0000
1024
pulses
XXXX X111 1111 1111
2047
pulses
Maximum possible number of pulses
7.9 Pulse Width Control
A register is used to define the duty cycle of the driver output signal. The default value for this register set during power up or power down (XPD
= LOW) is equal to 00h. In this case the default duty cycle of 50% is generated. The resulting duty cycle and resolution of single steps is
depending on the master clock frequency and the switching frequency of the driver output. Table 12 provides an example for 25MHz master
clock and 200kHz driver frequency. The value of the duty cycle register should not exceed 50.4% of the period counter value. Pulse Width
Modulation is used for speed control when motor is operating in half bridge mode.
Table 12. Pulse Width Register Values
Pulse Width Register
Typ
Unit
Conditions
0000 0000
49.6/50.4
%
default
0000 0001
0.8
%
0000 1101
10.4
%
0001 1011
21.6
%
0011 0101
42.4
%
0011 1110
49.6
%
0011 1111
50.4
%
If operating in half bridge mode, the pulse width can be used to adjust speed. At 50% the motor will operate at its maximum speed. To reduce the
speed, the pulse width may be reduced. However, below ~15%, there may not be enough energy in the signal to move the motor.
7.10 Phase Shift
A register is used to define the phase shift between the two phases of the driver output signal. The default value for this register set during power
up or power down (XPD = LOW) is equal to 00h. In this case the default phase shift of 90° is generated. The resulting phase shift and resolution
of single steps is depending on the master clock frequency and the switching frequency of the driver output. Table 13 provides an example for
25MHz master clock and 200kHz driver frequency. The value of the phase shift register should not exceed 50.4% of the period counter value.
Negative phase shift values are achieved by changing the direction bit: -160deg = 20deg and inverted direction bit.
Table 13. Phase Shift Register Values
Phase Shift Register
Typ
Unit
Conditions
0000 0000
90.5
deg
Default (Normal for both SQL and UTAF)
0000 0001
2.88
deg
0000 1101
37.44
deg
0000 1110
40.32
deg
0001 1111
89.28
deg
0010 0000
92.16
deg
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