NSD-2101 Datasheet, PDF (13/22 Pages) ams AG – Piezo Motor Driver ASIC for SQL-RV Series Reduced Voltage SQUIGGLE® RV and UTAF™ Motors

NSD-2101
Data Sheet - Detailed Description
7.11 Period Offset
Period Offset register defines the offset which is added to the period counter to shift the switching frequency. It also provides some additional
control bits.
This offset is only activated when frequency tracking is stopped. An offset has been provided as some types of motors operate better at slightly
below mechanical resonance. Table 14 provides an example for 25MHz master clock and 200kHz nominal driver frequency. Period offset is only
supposed to lower drive frequency.
Table 14. Period Offset Register Values
Period Offset Register
Typ
Unit
Conditions
0000 0000
0
%
Default, no change of drive frequency
0000 0001
-0.8
%
0000 0010
-1.6
%
0000 0111
-5.6
%
Maximum period offset
1000 0000
0
%
Idle mode enabled
0100 0000
0
%
Half bridge mode enabled
0010 0000
0
%
Hybrid speed control enabled
0001 0000
0
%
Increased dead time enabled
Idle mode reduces power consumption while preserving the most recent frequency calibration. To further reduce power, the XPD pin must be
pulled to ground.
7.12 Hybrid Speed Register
The hybrid speed register allows the average voltage as seen by the motor to be set from VDD to 2 x VDD. This provides a power efficient
method of reducing the speed of the motor. The value of the register can vary from 0 (half bridge) to 128 (full bridge). The average voltage can
be calculated in the following manner.
Where: VDD is the supply voltage
VAVG = VDD + (RegisterValue * VDD / 128)
(EQ 2)
Table 15. Hybrid Speed Register Values
Hybrid Speed Register
Typ
Unit
Conditions
0000 0000
0
%
VDD (half bridge)
0010 0000
25
%
VDD + 0.25 * VDD
0110 0000
75
%
VDD + 0.75 * VDD
1000 0000
100
%
VDD + VDD (full bridge)
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