NSD-2101 Datasheet, PDF (6/22 Pages) ams AG – Piezo Motor Driver ASIC for SQL-RV Series Reduced Voltage SQUIGGLE® RV and UTAF™ Motors

NSD-2101
Data Sheet - Detailed Description
7 Detailed Description
Figure 1 shows the main building blocks of the system:
Supply input
LDO and bypass capacitors
I²C interface
Registers
Oscillator
Frequency tracking
Full bridge driver
The input voltage is supplied directly to the full bridge driver. With a full bridge drive, each piezo element sees twice the input voltage (2 x VDD).
However, the average input voltage to the piezo can be regulated by the ASIC between VDD and 2 x VDD. This average voltage, which can be
set via I²C along with the duty cycle (or pulse width) of the drive signal, determines the speed of the motor. The result being at lower speeds, the
motor consumes less power.
I²C registers also define the initial switching frequency of the motor, which can be adjusted from 50 kHz to 200 kHz based on the type of motor
being driven. Other registers control motor direction and the number of pulses the motor is active (correlating to distance traveled). The XPD
input enables a stand-by mode.
7.1 Output Drivers
The output drivers operate rail to rail and are capable of driving capacitive load up to 60nF. The concept is based on two full bridges per motor.
The reduced voltage Squiggle motor consists of 2 plates per phase and 2 phases. In power down mode the output drivers are pulled to ground.
The same applies when the motor is off.
Table 6. Characteristics for Output Drivers
Symbol
Parameter
Conditions
Min
Typ
Max
Units
f_tr
Rise/fall time from 0.23V to 2.07V and
f_tf
vice versa
CLOAD 50nF,
VDD=2.3V¹
0.08
CLOAD
Load capacitance
10
I_lim
Current limit for driver outputs²
1000
0.8
µs
60
nF
1600
mA
f_DFR
Drive frequency range³
50
200
kHz
f_DC
Switching frequency duty cycle
1
50
%
t_DT
Dead time (additional)
VCO clock cycles⁴
2
4
9
f_PS
Phase shift
f_PSE
Phase shift error
-160
+90
deg
±3
deg
1. Measured at 10% to 90% of minimum VDD=2.3V. Maximum with 4 clocks dead-time.
2. Current limit is valid for full bridge and half bridge configuration. Due to the dynamic behavior of the output driver the maximum current
limit can not be reached under all conditions. Device can only be used for direct motor drive.
3. For this frequency range, frequency tracking is implemented.
4. Error of dead time is maximum +1 VCO clock cycle.
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