NSD-2101 Datasheet, PDF (11/22 Pages) ams AG – Piezo Motor Driver ASIC for SQL-RV Series Reduced Voltage SQUIGGLE® RV and UTAF™ Motors

NSD-2101
Data Sheet - Detailed Description
7.6 Control Register
The control register is used to trigger frequency calibration as well as to select and enable the drive phases.
Table 9. Control Register
Control Flag Mask
Abbr
Default
Description
1000 0000
0100 0000
0010 0000
PS[1]
PS[0]
0
Reserved (leave 0)
1
Phase Select for sensing: PS[1] PS[0]:
00=None
01=Phase1
1
10=Phase2
11= Both Phases
0001 0000
0000 1000
0000 0100
CN[1]
CN[0]
0
Reserved (leave 0)
0
Calibrate Now: CN[1] CN[0]:
00=None
01=Incremental
0
10=Sweep
11=reserved
0000 0010
P1
1
Enable Phase1
0000 0001
P2
1
Enable Phase2
7.7 Period Counter
The period counter is used to define the switching frequency of the motor. The pulse period is generated by dividing the internal VCO clock
frequency by the given period counter value. The MSB in the high byte of the pulse counter (p) is used as the MSB for the period counter.
At 25MHz clock a decimal period counter value of 125 gives an output frequency of 200 kHz. A period counter value of 126 results in a switching
frequency of 198.41 kHz. This is equal to a maximum frequency step of 1.59 kHz. The frequency resolution gets better for lower switching
frequencies assuming a fixed VCO clock frequency.
Table 10 lists out few examples to define period counter and output switching frequency relationship. The values are given for 25MHz typical
VCO clock frequency. The switch frequency is given as:
f_D = 25MHz / period counter value
(EQ 1)
Table 10. Period Counter Values
Period Counter Value
Typ
Unit
0 0111 1101
200.00
kHz
0 0111 1110
198.41
kHz
0 1001 0001
172.4
kHz
0 1010 0110
150.60
kHz
0 1010 0111
149.70
kHz
1 1111 0011
50.10
kHz
1 1111 0100
50.00
kHz
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