PALCE26V12 Datasheet, PDF (7/21 Pages) Advanced Micro Devices – 28-Pin EE CMOS Versatile PAL Device

AMD
LOGIC DIAGRAM
PALCE26V12
0
4
8
12
16
20
24
28
32
36
40
44
48
0
1
1
CLK ₁/I₀
9
2
I1
10
18
3
I₂
19
29
4
CLK ₂ /I ₃
30
42
5
I₄
43
57
6
I₅
58
74
8
I6
0
4
8
12
16
20
24
28
32
36
40
44
48
*When S₃ = 1 (unprogrammed) the feedback is selected by S₁.
When S3 = 0 (programmed), the feedback is the opposite of
that selected by S1.
ASYNCH.
RESET
AR
DQ
1
Q
0
SP
S2
0
1
10
11
00
01
S0
S1
R ₁₁
S3 ^*
28
I 13
27
I/O ₁₁
AR
DQ
1
Q
0
SP
S2
0
1
10
11
00
01
S0
S1
R
10
S3 ^*
26
I/O ₁₀
D ^ARQ
1
Q
0
SP
S2
0
1
10
11
00
01
S0
R9 ^S1
S3*
25
I/O ₉
10
D ^ARQ
1
Q
0
SP
S2
0
11
00
01
S0
R8 ^S1
1
S3 ^*
24
I/O 8
10
D ^ARQ
1
Q
0
SP
S2
0
11
00
01
S0
R ₇ ^S1
1
S3 ^*
23
I/O 7
10
DARQ
1
Q
0
SP
S2
11
00
01
S0
S1
0 ^R6
1
AR CLK₁
S3 ^*
SP CLK 2
22
I/O ₆
21
GND
16072E-6
2–312
PALCE26V12 Family