PALCE26V12 Datasheet, PDF (21/21 Pages) Advanced Micro Devices – 28-Pin EE CMOS Versatile PAL Device

AMD
fMAX Parameters
The parameter fMAX is the maximum clock rate at which
the device is guaranteed to operate. Because the flexi-
bility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, fMAX is specified for
three types of synchronous designs.
The first type of design is a state machine with feedback
signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the in-
put setup time for the external signals (tS + tCO). The re-
ciprocal, fMAX, is the maximum frequency with external
feedback or in conjunction with an equivalent speed de-
vice. This fMAX is designated “fMAX external.”
The second type of design is a single-chip state ma-
chine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop out-
puts. Under these conditions, the period is limited by the
internal delay from the flip-flop outputs through the inter-
nal feedback and logic to the flip-flop inputs. This fMAX is
designated “fMAX internal”. A simple internal counter is a
good example of this type of design, therefore, this pa-
rameter is sometimes called “fCNT.”
The third type of design is a simple data path applica-
tion. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (tS + tH). How-
ever, a lower limit for the period of each fMAX type is the
minimum clock period (tWH + tWL). Usually, this minimum
clock period determines the period for the third fMAX,
designated “fMAX no feedback.”
fMAX external and fMAX no feedback are calculated pa-
rameters. fMAX external is calculated from tS and tCO, and
fMAX no feedback is calculated from tWL and tWH. fMAX in-
ternal is measured.
CLK
LOGIC
REGISTER
(SECOND
CHIP)
t_S
t _CO
t_S
fMAX External; 1/(tS + tCO)
CLK
CLK
LOGIC
REGISTER
LOGIC
REGISTER
fMAX Internal (fCNT)
t_S
fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL)
16072E-18
2–326
PALCE26V12 Family