PALCE26V12 Datasheet, PDF (19/21 Pages) Advanced Micro Devices – 28-Pin EE CMOS Versatile PAL Device

AMD
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will
be reset to LOW after the device has been powered up.
The output state will depend on the programmed
configuration. This feature is valuable in simplifying
state machine initialization. A timing diagram and
parameter table are shown below. Due to the synchro-
nous operation of the power-up reset and the wide
Parameter
Symbol
tPR
tS
tWL
Parameter Description
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
range of ways VCC can rise to its steady state, two
conditions are required to ensure a valid power-up
reset. These conditions are:
The VCC rise must be monotonic.
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Max
Unit
1000
ns
See Switching
Characteristics
4V
VCC
Power
tPR
Registered
Active-Low
Output
tS
Clock
tWL
16072E-17
Power-Up Reset Waveform
2–324
PALCE26V12 Family