NPE405L Datasheet, PDF (7/54 Pages) Applied Micro Circuits Corporation – PowerNP

PowerNP NPe405L Embedded Processor Data Sheet
NPe405L Embedded Controller Functional Block Diagram
Preliminary
Universal
Interrupt
Controller
x2
8KB
D-Cache
Clock
Control
Reset
Power
Mgmt
Timers
MMU
PPC405
Processor Core
JTAG
DCU
Trace
ICU
DCRs
See Peripheral Interface
Clock Timing table
DCR Bus
GPIO IIC
UART
x2
16KB _Arb
I-Cache
On-chip Peripheral Bus (OPB)
DMA
Controller
(4-Channel)
OPB
Bridge
SDRAM
Controller
13-bit addr
32-bit data
Processor Local Bus (PLB)
MAL0
Ethernet
x2
External
Bus
Controller
28-bit addr
16-bit data
MAL1
HDLCEX
Two
32-channel
ports
ZMII
MII,
RMII,
SMII
The NPe405L is designed using the IBM Microelectronics Blue Logic methodology in which major functional
blocks are integrated to create an application-specific ASIC product. This approach provides a consistent way
to generate complex ASICs using IBM CoreConnect Bus Architecture.
Address Map Support
The NPe405L incorporates two separate address maps. The first is a fixed processor address map that
serves the PowerPC family of processors. This address map defines the possible contents of various address
regions which the processor can access. The second address map is for Device Configuration Registers
(DCRs). The DCRs are accessed by software running on the NPe405L processor through the use of mtdcr
and mfdcr commands.
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