NPE405L Datasheet, PDF (33/54 Pages) Applied Micro Circuits Corporation – PowerNP

PowerNP NPe405L Embedded Processor Data Sheet
Preliminary
that the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into
the NPe405L.
Unused I/Os
Strapping of some pins may be necessary when they are unused. Although the NPe405L requires only the
pull-up and pull-down terminations as specified in the “Signal Functional Description” on page 32, good
design practice is to terminate all unused inputs or to configure I/Os such that they always drive. If unused,
the peripheral and SDRAM bus should be configured and terminated as follows:
• Peripheral interface—PerAddr00:31, PerData00:31, and all of the control signals are driven by default.
Terminate PerReady high and PerError low.
• SDRAM—Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the NPe405L
to actively drive all of the SDRAM address, data, and control signals.
External Peripheral Bus Control Signals
All external peripheral bus control signals (PerCS0:3, PerR/W, PerWBE0:1, PerOE, PerWE, PerBLast) are
set to the high-impedance state when ExtReset=0. In addition, as detailed in the PowerNP NPe405L
Embedded Processor User’s Manual, the peripheral bus controller can be programmed via EBC0_CFG to
float some of these control signals between transactions. As a result, a pull-up resistor should be added to
those control signals where an undriven state may affect any devices receiving that particular signal.
The following table lists all of the I/O signals provided by the NPe405L. Please see “Signals Listed
Alphabetically” on page 13 for the pin number to which each signal is assigned. In cases where a multiplexed
signal (indicated by the square brackets) is shown without the other signals that are assigned to that pin, you
can see what the other signals are by referring to the same table.
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