NPE405L Datasheet, PDF (38/54 Pages) Applied Micro Circuits Corporation – PowerNP

Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description (Part 5 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 31.
Signal Name
UART1_Rx
UART1_Tx
[UART1_DCD]
[UART1_DSR]
[UART1_CTS]
[UART1_DTR]
[UART1_RTS]
[UART1_RI]
IICSCL
IICSDA
Interrupts Interface
[IRQ0:6]
JTAG Interface
TDI
TMS
TDO
TCK
TRST
Description
UART1 Receive data.
UART1 Transmit data.
UART1 Data Carrier Detect.
UART1 Data Set Ready.
UART1 Clear To Send.
UART1 Data Terminal Ready.
UART1 Request To Send.
UART1 Ring Indicator.
IIC Serial Clock.
IIC Serial Data.
I/O
Type
I
5V tolerant
3.3V LVTTL
O
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
O
5V tolerant
3.3V LVTTL
O
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
I/O
5V tolerant
3.3V LVTTL
I/O
5V tolerant
3.3V LVTTL
Interrupt Requests.
I
5V tolerant
3.3V LVTTL
Test Data In.
Test Mode Select.
Test Data Out.
Test Clock.
Test Reset. TRST must be low at power-on to reset the
JTAG boundary scan state machine.
I
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
O
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
Notes
1
6
1, 4
1, 4
1, 4
6
6
1, 4
1, 2
1, 2
1
1, 4
1, 4
1, 4
5
36