NPE405L Datasheet, PDF (40/54 Pages) Applied Micro Circuits Corporation – PowerNP

Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device.
Characteristic
Symbol
Value
Unit
Supply Voltage (Internal Logic)
V_DD
Supply Voltage (I/O Interface)
OV_DD
PLL Supply Voltage ²
AV_DD
Input Voltage (3.3V LVTTL receivers)
V_IN
Input Voltage (5.0V LVTTL receivers)
V_IN
Storage Temperature Range
T_STG
Case temperature under bias
T_C
Notes:
1. All voltages are specified with respect to ground (GND).
2. AV_DD should be derived from V_DD using the following circuit:
0 to +2.7
V
0 to +3.6
V
0 to +2.7
V
-0.6 to (OV_DD + 0.6)
V
-0.6 to (OV_DD + 2.4)
V
-55 to +150
°C
-40 to +120
°C
V_DD
L1
AV_DD
L1 – 2.2µH SMT inductor (equivalent to MuRata
LQH3C2R2M34) or SMT chip ferrite bead (equivalent
to MuRata BLM31A700S)
C1
C2
C3
C1 – 3.3 µF SMT tantalum
C2 – 0.1µF SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
C3 – 0.01 µF SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
Package Thermal Specifications
The NPe405L is designed to operate within a case temperature range of -40°C to 85°C. Thermal resistance values for the
E-PBGA packages in a convection environment are as follows:
Package—Thermal Resistance
Symbol
Airflow
ft/min (m/sec)
Unit
0 (0)
100 (0.51)
200 (1.02)
23mm, 324-balls—Junction-to-Case
θ_JC
2
2
2
°C/W
23mm, 324-balls—Case-to-Ambient¹
θ_CA
17
15
14
°C/W
Notes:
1. For a chip mounted on a JEDEC 2S2P card without a heat sink.
2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:
a. Case temperature, T_C, is measured at top center of case surface with device soldered to circuit board.
b. T_A = T_C – P×θ_CA, where T_A is ambient temperature and P is power consumption.
c. T_CMax = T_JMax – P×θ_JC, where T_JMax is maximum junction temperature and P is power consumption.
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