NPE405L Datasheet, PDF (52/54 Pages) Applied Micro Circuits Corporation – PowerNP

Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
I/O Specifications—266MHz (Part 2 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM. Output times in table are in cycle 1.
3. SDRAM I/O timings are specified relative to a SysClk terminated in a lumped 10pF load.
4. SDRAM interface hold times are guaranteed at the NPe405L package pin. System designers must use the NPe405L
IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes loading and
reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns)
Signal
Setup Time Hold Time
(T_IS min) T_IH min)
Trace Interface
[TrcClk]
n/a
n/a
[TS1E]
n/a
n/a
[TS2E]
n/a
n/a
[TS1O]
n/a
n/a
[TS2O]
n/a
n/a
[TS3:6]
n/a
n/a
SDRAM Interface
BA1:0
n/a
n/a
BankSe3:0
n/a
n/a
CAS
n/a
n/a
ClkEn0:1
n/a
n/a
DQM0:3
n/a
n/a
DQMCB
n/a
n/a
ECC0:7
1.8
0.3
MemAddr12:00
n/a
n/a
MemClkOut0:1
n/a
n/a
MemData00:31
1.8
0.3
RAS
n/a
n/a
WE
n/a
n/a
External Peripheral Bus Interface
[DMAReq0:3]
4.1
0
[DMAAck0:3]
n/a
n/a
[EOT0:3/TC0:3]
3.7
-0.1
PerAddr04:31
n/a
n/a
PerBLast
n/a
n/a
PerCS0:3
n/a
n/a
PerData00:15
3.9
1
PerOE
n/a
n/a
PerPar0:1
2.7
0
PerR/W
n/a
n/a
PerReady
6.2
-0.5
PerWBE0:1
n/a
n/a
PerClk
n/a
n/a
PerErr
3.5
-0.6
[PerWE]
n/a
n/a
Output (ns)
Valid Delay Hold Time
(T_OV max) (T_OH min)
8.7
1.2
5.8
1.2
5.7
1.2
5.3
1
5.3
1
5.4
1
5.5
1.5
4.6
1
5.3
1.4
3.9
1
4.7
1
4.7
1
4.5
1
5.5
1.4
0.4
-1.2
4.4
1
5.7
1.6
5.4
1.4
5.5
1.1
5.9
1.1
6.7
1.2
6.5
0.9
5.6
1.4
5.5
1.3
7.1
1
5.7
1.4
6.4
0.9
5.7
1.4
n/a
n/a
5.7
1.3
0.5
-0.9
n/a
n/a
7
1.3
Output Current (mA)
I/O H
I/O L
(maximum) (minimum)
12
8
12
8
12
8
12
8
12
8
12
8
19
12
19
12
19
12
40
25
19
12
19
12
19
12
19
12
19
12
19
12
19
12
19
12
n/a
n/a
12
8
12
8
17
11
12
8
12
8
17
11
12
8
17
11
12
8
n/a
n/a
12
8
17
11
n/a
n/a
12
8
Clock
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PLB Clk
PerClk
Notes
1, 2
2
1, 2
2
2
2
2
1, 2
2, 3
2
1, 2
1, 2
4
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