NPE405L Datasheet, PDF (36/54 Pages) Applied Micro Circuits Corporation – PowerNP

Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description (Part 3 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 31.
Signal Name
Description
I/O
ECC0:7
ECC check bits 0:7.
I/O
BankSel0:3
Select up to four external SDRAM banks.
O
WE
Write Enable.
O
ClkEn0:1
SDRAM Clock Enable.
O
MemClkOut0:1
Two copies of an SDRAM clock allows, in some cases,
glueless SDRAM attachment without requiring this signal
O
to be repowered by a PLL or zero-delay buffer.
External Peripheral Bus Interface
PerData00:15
External peripheral data bus .
Note: PerData00 is the most significant bit (msb) on this
I/O
bus.
PerAddr04:31
External peripheral address bus .
O
PerPar0:1
PerWBE0:1
[PerWE]
PerCS0:3
PerOE
PerR/W
External peripheral byte parity signals.
I/O
Peripheral write-bte enable. Byte-enables which are valid
for an entire cycle or write-byte-enables which are valid for
each byte on each data transfer, allowing partial word
O
transactions. Used by either external bus controller or DMA
controller depending upon the type of transfer involved.
Peripheral write enable. Low when any of the two PerWBE
signals are low.
I/O
Peripheral Chip Selects
O
Peripheral output enable. Used by either the external bus
controller or the DMA controller depending upon the type
of transfer involved. When the NPe405L is the bus master,
O
it enables the peripherals to drive the bus.
Peripheral read/write. Used by either the external bus
controller or DMA controller depending upon the type of
transfer involved. High indicates a read from memory, low O
indicates a write to memory.
Type
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
Notes
1
1
2, 7
7
7
PerReady
PerBLast
PerClk
PerErr
Indicates peripheral is ready to transfer data.
I
5V tolerant
3.3V LVTTL
1
Peripheral burst last. Used to indicate the last transfer of a
memory access.
O
5V tolerant
3.3V LVTTL
7
Peripheral Clock. Used by synchronous peripherals.
O
5V tolerant
3.3V LVTTL
Used to indicate errors from peripherals.
I
5V tolerant
3.3V LVTTL
1, 5
34