EPF10K50VQC240-3 Datasheet, PDF (99/128 Pages) Altera Corporation – Embedded Programmable Logic Device Family

FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Notes to tables:
(1) All timing parameters are described in Tables 32 through 38 in this data sheet.
(2) Using an LE to register the signal may provide a lower setup time.
(3) This parameter is specified by characterization.
Tables 85 through 91 show EPF10K10A device internal and external
timing parameters.
Table 85. EPF10K10A Device LE Timing Microparameters Note (1)
Symbol
t_LUT
t_CLUT
t_RLUT
t_PACKED
t_EN
t_CICO
t_CGEN
t_CGENR
t_CASC
t_C
t_CO
t_COMB
t_SU
t_H
t_PRE
t_CLR
t_CH
t_CL
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
0.9
1.2
1.6
ns
1.2
1.4
1.9
ns
1.9
2.3
3.0
ns
0.6
0.7
0.9
ns
0.5
0.6
0.8
ns
02
0.3
0.4
ns
0.7
0.9
1.1
ns
0.7
0.9
1.1
ns
1.0
1.2
1.7
ns
1.2
1.4
1.9
ns
0.5
0.6
0.8
ns
0.5
0.6
0.8
ns
1.1
1.3
1.7
ns
0.6
0.7
0.9
ns
0.5
0.6
0.9
ns
0.5
0.6
0.9
ns
3.0
3.5
4.0
ns
3.0
3.5
4.0
ns
Table 86. EPF10K10A Device IOE Timing Microparameters Note (1) (Part 1 of 2)
Symbol
t_IOC
t_IOCO
t_IOCOMB
t_IOSU
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
1.3
1.5
2.0
ns
0.2
0.3
0.2
0.3
0.6
0.7
0.8
1.0
1.3
0.3
ns
0.4
ns
0.9
ns
ns
Altera Corporation
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