EPF10K50VQC240-3 Datasheet, PDF (119/128 Pages) Altera Corporation – Embedded Programmable Logic Device Family

FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Notes to tables:
(1) All timing parameters are described in Tables 32 through 37 in this data sheet.
(2) Using an LE to register the signal may provide a lower setup time.
(3) This parameter is specified by characterization.
ClockLock &
ClockBoost
Timing
Parameters
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock during configuration. The circuit will be ready for use immediately
after configuration. Figure 31 illustrates the incoming and generated clock
specifications.
Figure 31. Specifications for the Incoming & Generated Clocks
The t_I parameter refers to the nominal input clock period; the t_O parameter refers to the
nominal output clock period.
tCLK1
tINDUTY
tI ± fCLKDEV
Input
Clock
tR t_F
tOUTDUTY
tI
tI ± tINCLKSTB
ClockLock-
Generated
Clock
tO
tO + tJITTER tO – tJITTER
Table 113 summarizes the ClockLock and ClockBoost parameters.
Table 113. ClockLock & ClockBoost Parameters (Part 1 of 2)
Symbol
Parameter
t_R
t_F
t _INDUTY
f _CLK1
t _CLK1
f_CLK2
t_CLK2
Input rise time
Input fall time
Input duty cycle
Input clock frequency (ClockBoost clock multiplication factor equals 1)
Input clock period (ClockBoost clock multiplication factor equals 1)
Input clock frequency (ClockBoost clock multiplication factor equals 2)
Input clock period (ClockBoost clock multiplication factor equals 2)
Min Typ Max Unit
2
ns
2
ns
45
55
%
30
80 MHz
12.5
33.3 ns
16
50 MHz
20
62.5 ns
Altera Corporation
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