EPF10K50VQC240-3 Datasheet, PDF (30/128 Pages) Altera Corporation – Embedded Programmable Logic Device Family

FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 13. Bidirectional I/O Registers
Row and Column 2 Dedicated
Interconnect Clock Inputs
4 Dedicated Peripheral
Inputs
Control Bus
2
4
12
OE Register
DQ
VCC
ENA
CLRN
VCC
OE[7..0]
Chip-Wide
Reset
Chip-Wide
Output Enable
VCC
CLK[1..0]
CLK[3..2]
VCC
ENA[5..0]
VCC
CLRN[1..0]
Output Register
DQ
ENA
CLRN
VCC
Chip-Wide
Reset _{Input Register}
DQ
ENA
CLRN
Open-Drain
Output
Slew-Rate
Control
Chip-Wide
Reset
30
Altera Corporation