EPF10K50VQC240-3 Datasheet, PDF (16/128 Pages) Altera Corporation – Embedded Programmable Logic Device Family

FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 7 shows how an n-bit full adder can be implemented in n + 1 LEs
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can either be bypassed for simple adders or
be used for an accumulator function. The carry chain logic generates the
carry-out signal, which is routed directly to the carry-in signal of the next-
higher-order bit. The final carry-out signal is routed to an LE, where it can
be used as a general-purpose signal.
Figure 7. Carry Chain Operation (n-bit Full Adder)
Carry-In
a1
LUT
Register
s1
b1
Carry Chain
LE1
a2
LUT
Register
s2
b2
Carry Chain
LE2
an
LUT
Register
sn
bn
Carry Chain
LEn
LUT
Carry Chain
Register
Carry-Out
LEn + 1
16
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