EPF10K50VQC240-3 Datasheet, PDF (60/128 Pages) Altera Corporation – Embedded Programmable Logic Device Family

FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Table 32. LE Timing Microparameters (Part 2 of 2) Note (1)
Symbol
t_SU
t_H
t_PRE
t_CLR
t_CH
t_CL
Parameter
LE register setup time for data and enable signals before clock; LE register
recovery time after asynchronous clear, preset, or load
LE register hold time for data and enable signals after clock
LE register preset delay
LE register clear delay
Minimum clock high time from clock pin
Minimum clock low time from clock pin
Conditions
Table 33. IOE Timing Microparameters Note (1)
Symbol
t_IOD
t_IOC
t_IOCO
t_IOCOMB
t_IOSU
t_IOH
t_IOCLR
t_OD1
t_OD2
t_OD3
t_XZ
t_ZX1
t_ZX2
t_ZX3
t_INREG
t_IOFD
t_INCOMB
Parameter
Conditions
IOE data delay
IOE register control signal delay
IOE register clock-to-output delay
IOE combinatorial delay
IOE register setup time for data and enable signals before clock; IOE register
recovery time after asynchronous clear
IOE register hold time for data and enable signals after clock
IOE register clear time
Output buffer and pad delay, slow slew rate = off, V_CCIO = V_CCINT
Output buffer and pad delay, slow slew rate = off, V_CCIO = low voltage
Output buffer and pad delay, slow slew rate = on
C1 = 35 pF (2)
C1 = 35 pF (3)
C1 = 35 pF (4)
IOE output buffer disable delay
IOE output buffer enable delay, slow slew rate = off, V_CCIO = V_CCINT
IOE output buffer enable delay, slow slew rate = off, V_CCIO = low voltage
IOE output buffer enable delay, slow slew rate = on
C1 = 35 pF (2)
C1 = 35 pF (3)
C1 = 35 pF (4)
IOE input pad and buffer to IOE register delay
IOE register feedback delay
IOE input pad and buffer to FastTrack Interconnect delay
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