EP4SGX180DF29I3N Datasheet, PDF (69/82 Pages) Altera Corporation – Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–61
Table 1–49 lists the memory output clock jitter specifications for Stratix IV devices.
Table 1–49. Memory Output Clock Jitter Specification for Stratix IV Devices ⁽¹⁾, ⁽²⁾, ⁽³⁾
Parameter
Clock
Network
Symbol
–2/–2X
Speed Grade
Min Max
–3
Speed Grade
Min Max
–4
Speed Grade
Unit
Min Max
Clock period jitter
Regional
t_JIT(per)
-50
50
-55
55
-55
55
ps
Cycle-to-cycle period jitter Regional t_JIT(cc)
-100
100
-110
110
-110
110
ps
Duty cycle jitter
Regional
t_JIT(duty)
-50
50
-82.5 82.5 -82.5 82.5 ps
Clock period jitter
Global
t_JIT(per)
-75
75
-82.5 82.5 -82.5 82.5 ps
Cycle-to-cycle period jitter Global
t_JIT(cc)
-150
150
-165
165
-165
165
ps
Duty cycle jitter
Global
t_JIT(duty)
-75
75
-90
90
-90
90
ps
Notes to Table 1–49:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL
output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible.
(3) The memory output clock jitter stated in Table 1–49 is applicable when an input jitter of 30 ps is applied.
OCT Calibration Block Specifications
Table 1–50 lists the OCT calibration block specifications for Stratix IV devices.
Table 1–50. OCT Calibration Block Specifications for Stratix IV Devices
Symbol
Description
Min
OCTUSRCLK Clock required by OCT calibration blocks
—
T_OCTCAL
Number of OCTUSRCLK clock cycles required for OCT R_S/R_T
calibration
—
T_OCTSHIFT
Number of OCTUSRCLK clock cycles required for OCT code
to shift out
—
T_{RS_RT}
Time required between the dyn_term_ctrl and oe signal
transitions in a bidirectional I/O buffer to dynamically switch
—
between OCT R_S and R_T
Typ
—
1000
28
2.5
Max
Unit
20
MHz
— Cycles
— Cycles
—
ns
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum